1. Field of the Invention
The present invention relates generally to a chip stack package. More particularly, the present invention relates to a chip stack package using a dummy pattern die.
2. Description of the Prior Art
As generally known in the art, the semiconductor packaging technologies have been focusing on ways to mount a greater number of chips or packages on a package substrate having a predetermined size that have also been reduced over time. In addition, recently, as the size of the package becomes reduced, the studies have been actively performed in relation to a chip stack package capable of mounting two to four semiconductor chips on one package.
Currently available packaging techniques are the FBGA package, the MCP (multi chip package), and the DDP (double die package), all of which make an electrical interconnection between a chip and a substrate by using a wire bonding. However, in such a package, the bonding pads 1a, 2a and 3a (now referring to FIG. 1, which is a top view showing the stacked chips 1, 2, and 3 without the substrate 6 shown in FIG. 2) extend in one direction on top of each respective stacked chip 1, 2, or 3, such that the number of bonding wires 4 is increased. For this reason, as shown in FIG. 2, the bonding wires 4 run in the horizontal and/or the vertical direction in order to prevent the stacked chips 1, 2, and 3 from interfering with each other during the wire bonding process; however, this causes the size of a substrate 6 to become enlarged. Enlarged size of the substrate 6 will increase the overall size of the package. Each bonding wire is connected between two boding fingers 7, and any two stacked chips 1, 2, or 3 are joined with adhesive 5.
FIG. 3 shows the prior art solution to the above-discussed prior art problem, which proposes a method of making an electrical interconnection between the semiconductor chips 1, 2, and 3 and the substrate 6 by using a metal film tape 10, instead of using the wire bonding (such as FIG. 2, elements 4). However, when the metal film tape 10 is drawn in one direction, extra space is necessary in order to prevent the semiconductor chips 1, 2, and 3 from interfering with each other. Thus, even in the case of the prior art solution as shown in FIG. 3, the length of the metal film tape 10 must be increased, so that the size of the package is also enlarged.